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DATA SHEET
MOS INTEGRATED CIRCUIT
PD17P207
4-BIT SINGLE-CHIP MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND A/D CONVERTER FOR INFRARED REMOTE CONTROL TRANSMITTER
DESCRIPTION
PD17P207 is a variation of PD17207 and is equipped with a one-time PROM instead of an internal mask
ROM.
PD17P207 is suitable for evaluating program when developing a PD17201A and 17207 systems because
program can be written by the user. When reading this document, also refer to the PD17201A, 17207 documents.
FEATURES
* 17K architecture: General-purpose register format * Pin-compatible with PD17201A, 17207 except PROM programming functiom * Internal one-time PROM: 4096 x 16 bits * Supply voltage: 2.5 to 5.5 V (at fX = 4 MHz, TA = -20 to +75C) 2.4 to 5.5 V (at fX = 4 MHz, TA = -20 to +60C) 2.0 to 5.5 V (at fXT = 32.768 kHz, TA = -20 to +75C)
ORDERING
INFORMATION
Package 80-pin plastic QFP (14 x 20 mm) 80-pin plastic QFP (14 x 20 mm) 80-pin plastic QFP (14 x 20 mm)
Part Number
PD17P207GF-001-3B9 PD17P207GF-002-3B9 PD17P207GF-003-3B9
The features of each product is shown in the following table: When using PD17P207-001, be sure to connect the resonator to the main clock oscllator circuit and subclock oscillator circuit.
Item Pull-up resistor of RESET pin Main clock oscillator circuit Subclock oscillator circuit
PD17P207-001
Provided
PD17P207-002 Not provided Provided Not provided
PD17P207-003 PD17201A, 17207
Not provided Provided On request (mask option)
PD17P207 is different from PD17201A, 17207 in some of the electrical characteristics, such as
supply voltage, the operating ambient temperature, and supply current. Therefore, use PD17P207 only for the system evaluation.
The information in this document is subject to change without notice.
Document No. U11777EJ3V0DS00 (3rd edition) Previous No. IC-2707A Date Published November 1996 P Printed in Japan
The mark
shows major revised points.
(c)
1993
PD17P207
PIN CONFIGURATION (TOP VIEW)
(1) Ordinary operation mode
LCD34/COM3
LCD35/COM2
WDOUT
LCD32 LCD31 LCD30 LCD29 LCD28 LCD27 LCD26 LCD25 LCD24 LCD23 LCD22 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 LCD14 LCD13 LCD12 LCD11 LCD10 LCD9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 1 2 3 4 5 6 7 8 63 62 61 60 59 58 57
RESET
CAPH
COM1
COM0
LCD33
CAPL
XTOUT
VLCDC
VLCD2
VLCD1
VLCD0
VREG
XTIN
XOUT XIN VDD REM P1A2/SI P1A1/SO P1A0/SCK P0D3 P0D2 P0D1/TMOUT P0DO/LED P0C3 P0C2 P0C1 P0C0 P0B3 P0B2 P0B1 P0B0 P0A3 P0A2 P0A1 P0A0 INT
PD17P207GF-3B9
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2
GNDADC
ADC 0
ADC1
ADC2
ADC3
LCD8
LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
GND
VADC
PD17P207
(2) PROM programming mode
(OPEN)
(L)
(OPEN) (L)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 1 2 3 4 5 6 7 8 63 62 61 60 59 58 57
(OPEN) CLK VDD (OPEN)
(L)
PD17P207GF-3B9
9 10 11 12
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42
D7 D6 D5 D4 MD 3 MD 2 MD 1 MD 0 D3 D2 D1 D0 VPP
(OPEN)
13 14 15 16 17 18 19 20 21 22 23
41 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(OPEN) VDD
GND
(OPEN)
Caution: Those enclosed in parentheses indicate the processing of the pins not used in PROM programming mode. L : Ground these pins through a resistor (470 ). Open : Do not connect anything to these pins.
GNDADC
(L)
3
PD17P207
Pin Name ADC0-ADC3 CLK COM0-COM3 D0-D7 INT LCD0-LCD35 LED MD0-MD3 P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 REM RESET SCK SI SO TMOUT VADC VDD VLCD0-VLCD2 VLCDC VPP VREG WDOUT XIN, XOUT XTIN, XTOUT : A/D converter input : PROM clock input : LCD common signal output : PROM data I/O : External interrupt request signal input : LCD segment signal output : Remote controller transfer display output : PROM mode selection input : I/O port : I/O port : I/O port : I/O port : Remote controller transfer output : Reset signal input : Serial clock I/O : Serial data input : Serial data output : Timer output : A/D converter power supply : Power supply : LCD drive voltage output : LCD drive reference voltage adjustment : PROM writing power supply : Voltage regulator output : Overrun detection output : Main clock oscillator circuit : Subclock oscillator circuit
CAPH, CAPL : Booster capacitor connection
GND, GNDADC : Ground
4
PD17P207
BLOCK DIAGRAM
VREG VDD CAPH CAPL VLCD0 VLCD1 VLCD2 VLCDC GMD LCD0 LCD1 LCD2 LCD3 LCD4 LCD33 COM3/LCD34 COM2/LCD35 COM1 COM0
Power Supply Circuit P1A0 SCK P1A1/SO P1A2/SI P1A
RF
Serial Interface
RAM 336 x 4 bits SYSTEM REG.
LCD
Controller
P0A0 (D0) P0A1 (D1) P0A2 (D2) P0A3 (D3)
P0A ALU
P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3)
P0B
Instruction Decoder
Interrupt Controller
INT (Vpp )
P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7)
One Time PROM P0C 4096 x 16 bits
A/D Converter
VADC ADC0 ADC1 ADC2 ADC3
P0D0/LED P0D1/TMOUT P0D2 P0D3
P0D Program Counter Stack 5 x 12 bits Carrier Generator
GNDADC RESET WDOUT CPU Clock Clock Stop X IN (CLK) Main clock
REM
Timer/ Counter
XOUT Watch Timer Divider CPU Clock XTIN Subclock XTOUT
Remark
Inside the parenthesis indicates pin names in the PROM programming mode.
5
PD17P207
CONTENTS
1.
PIN FUNCTIONS ................................................................................................................................. 7
1.1 1.2 1.3 1.4 1.5 ORDINARY OPERATION MODE .............................................................................................................. 7 PROM PROGRAMMING MODE ................................................................................................................ 9 EQUIVALENT CIRCUITS OF PINS ......................................................................................................... 10 PROCESSING OF UNUSED PINS .......................................................................................................... 11 NOTES ON USING RESET AND INT PINS (ONLY IN ORDINARY OPERATION MODE) ................... 12
2.
ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION ............... 13
2.1 2.2 2.3 OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY ..... 13 PROGRAM MEMORY WRITE PROCEDURE ......................................................................................... 14 PROGRAM MEMORY READ PROCEDURE ........................................................................................... 15
3. 4. 5. 6.
DEFFERENCES BETWEEN PD17P207 AND PD17201A/17207 ................................................. 16 ELECTRICAL CHARACTERISTICS ................................................................................................. 17 PACKAGE DRAWINGS .....................................................................................................................25 RECOMMENDED SOLDERING CONDITIONS ................................................................................ 26
APPENDIX A. MICROCONTROLLER FAMILY FOR HIGH-FUNCTION REMOTE CONTROLLER WITH LCD ........................................................................................................................27 APPENDIX B. DEVELOPMENT TOOLS ................................................................................................ 28
6
PD17P207
1.
1.1
PIN FUNCTIONS
ORDINARY OPERATION MODE
Symbol COM0 COM1 LCD35/COM2 LCD34/COM3 LCD33 LCD32 | LCD1 LCD0 GND VADC Function Common/segment signal outputs of the LCD driver. These common and segment signal outputs are selected by LCDMD3 to LCDMD0 of the register file. * COM0 to COM3 * Common signal outputs of the LCD driver * LCD35 to LCD0 * Segment signal outputs of the LCD driver Output Type On Reset
Pin No. 76 77 78 79 80 1 | 32 34 33 35
CMOS, push-pull
-
Device ground Positive power supply of the A/D converter (VADC should be equal to VDD.)
- -
- -
36 | 39 40
ADC0 | ADC3 GNDADC
Analog inputs of the A/D converter (8-bit resolution)
-
-
Ground of the A/D converter External interrupt request signal (Input). The interrupt request is generated at the rising edge of this signal.
- -
- Input
41
INT
42 | 45 46 | 49 50 | 53
P0A0 | P0A3 P0B0 | P0B3 P0C0 | P0C3
4-bit I/O port (enabling setting of inputs or outputs in 4-bit units) (Grouped I/O). Each of these pins has a pull-up resistor. 4-bit I/O port (enabling setting of inputs or outputs in 4-bit units) (Grouped I/O).
CMOS, push-pull
Input
N-channel, open-drain
Input
4-bit I/O port (enabling setting of inputs or outputs in 4-bit units) (Grouped I/O).
N-channel, open-drain
Input
54 55 56 57
P0D0/LED P0D1/TMOUT P0D2 P0D3
Port 0D/LED output or 8-bit timer output. P0D0 and LED outputs are switched by NRZEN of the register file. P0D1 and 8-bit timer outputs are switched by TMOE of the register file. * P0D0 to P0D3 * 4-bit I/O port * Enabling setting of inputs or outputs of each bit (Bitwise I/O) * LED * Outputs NRZ signal in synchronization with infrared remote controller signal (REM) * Outputs high level while remote controller carrier is output from REM pin * TMOUT * Output of the 8-bit timer
CMOS, push-pull
Input
(to be cont'd)
7
PD17P207
(cont'd) Pin No. Symbol Function Port 1A or serial interface. Port 1A and serial interface are switched by SIOEN of the register file. * P1A0 to P1A2 * 3-bit I/O port * Enabling setting of inputs or outputs of 3 bits (Grouped I/O) * SCK, SO, SI * SCK: Serial clock I/O * SO: Serial data output * SI: Serial data input Signal output to an infrared remote controller. Active-high output Positive power supply. These pins are connected to a 4-MHz ceramic or crystal resonator for main clock oscillation. System reset input System is reset when low level is input to this pin. While this pin is low, oscillation of main clock is stopped. Only PD17P207-001 has internal pull-up resistor. Output of the voltage regulator for the subclock oscillation circuit. Connect external 0.1-F capacitor to this pin. Output for detection of a program overrun. Outputs low level when the watchdog timer overflows or the stack overflows/underflows. Use this pin after connecting to the RESET pin. These pins are connected to a 32.768-kHz crystal oscillator - 69 71 70 72 73 XTOUT VLCDC VLCD0 VLCD1 VLCD2 for subclock oscillation. Input to regulate the reference voltage to drive LCD. Reference voltage outputs to drive LCD. * VLCD0: Reference voltage output * VLCD1: Doubler output (Two times the reference voltage) * VLCD2: Tripler output (Three times the reference voltage) 74 75 CAPH CAPL These pins are connected to a capacitor to boost the - LCD drive voltage. - - - - - (Oscillates.) Output Type On Reset
58 59 60
P1A0/SCK P1A1/SO P1A2/SI
CMOS, push-pull
Input
61
REM
CMOS, push-pull -
Low-level output - (Oscillation stops.)
62 63 64
VDD XIN XOUT
65
RESET
-
Input
66
VREG
-
-
67
WDOUT
N-channel, open drain
Highimpedance
68
XTIN
8
PD17P207
1.2 PROM PROGRAMMING MODE
Symbol GND VDD GNDADC Ground Positive power supply Ground for A/D converter Performs PROM programming with GNDADC = GND. Positive power supply for PROM programming. Applies 12.5V as the program voltage when writing, reading, and verifying the program memory. Function Output Type - - - On Reset - - -
Pin No. 33 35 40
41
VPP
-
-
42 to 45 50 to 53 46 to 49 62 63
D0 to D3 D4 to D7 MD0 to MD3 VDD CLK
8-bit data I/O for PROM programming.
CMOS, push-pull
Input
Select operation mode for PROM programming.
-
Input
Positive power supply Address update clock input
- -
- Input
Remark
Pins other than the above are not used in the PROM programming mode. For the processing of unused pins, refer to (2) PROM programming mode in PIN CONFIGURATION.
9
PD17P207
1.3 EQUIVALENT CIRCUITS OF PINS The followings are equivalent circuits (partially simplified) of the respective pins of the PD17P207. (1) P0A
VDD Output latch VDD Output latch
(4)
P0D, P1A
VDD
data
P-ch
data
P-ch
output disable Selector Input buffer
N-ch
output disable Selector Input buffer
N-ch
(2)
P0B
(5)
RESET
data
Output latch
VDD Pull-up resistor Note
output disable
N-ch Input buffer Input buffer Schmitt trigger input with hysteresis characteristics
Note
Only PD17P207-001 has the internal pull-up resistor.
(3)
P0C
(6)
INT
data
Output latch
output disable Selector Input buffer
N-ch
Input buffer Schmitt trigger input with hysteresis characteristics
10
PD17P207
1.4 PROCESSING OF UNUSED PINS In ordinay operation mode, process unused pins as follows:
Table 1-1. Processing of Unused Pins
(a) Port pins
Recommended Processing of Unused Pins Pin Name Internally Input Mode P0A P0C P0D, P1A (Connect pull-up resistor.) - - Open Directly connect to GND. Connect each pin to VDD or GND via resistorNote. Open Externally
Output Mode
P0A (CMOS port) P0D, P1A (CMOS port) P0B, P0C (N-ch open-drain port)
Outputs high level - Outputs low level
Note
When externally pulling a pin up (connecting the pin to VDD via resistor) and down (connecting the pin to GND via resistor), give adequate consideration to the drive capability and current consumption of the port. To pull a pin up or down at a high resistance, make sure that no noise is superimposed on the pin.
(b)
Pins other than port pins
Pn Name I/O Mode Input Output Output Input Output Output - Output - Output Input - - Recommended Processing of Unused Pin Directly connect to GND Open Open Directly connect to GND Open Open Directly connect to VDD Open Directly connect to VDD or VLCD0 Directly connect to GND Directly connect to GND Directly connect to VDD Directly connect to VREG
ADC0-ADC3 CAPH, CAPL COM0, COM1, COM2/LCD35, COM3/LCD34 INT
Note
LCD0-LCD33 REM VADC VLCD0-VLCD2 VLCDC WDOUT XIN, XTIN XOUT XTOUT
Note
The INT pin is also used as a test mode setting pin. Directly connect this pin to GND when it is not used.
Cautions 1. It is recommended that the input/output mode and output level of a pin be fixed by repeatedly setting in each loop of the program. 2. When the LCD controller/driver is not used, stop the voltage regulator by using the display mode register. 11
PD17P207
1.5 NOTES ON USING RESET AND INT PINS (ONLY IN ORDINARY OPERATION MODE) In addition to the functions shown in 1. PIN FUNCTIONS, the RESET and INT pins also have a function to set a test mode (for IC testing) in which the internal operations of the PD17P207are tested. When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the PD17P207 may be set in the test mode if a noise exceeding VDD is applied. For example, if the wiring length of the RESET or INT pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. * Connect diode with low VF between VDD and RESET/INT pin
V DD
* Connect capacitor between VDD and RESET/INT pin
V DD
Diode with low V F RESET, INT
V DD
V DD
RESET, INT
12
PD17P207
2. ONE-TIME PROM (PROGRAM MEMORY) WRITING, READING, AND VERIFICATION
PD17P207 sets the PROM mode when PROM writing, reading or verification as shown in Table 2-1.
In PROM mode, no address input pin is used. Instead, the address is updated by the clock for input from the CLK pin.
Table 2-1. Pins Used for Program Memory Writing, Reading, or Verification
Pin Name VPP CLK MD0-MD3 D0-D7 VDD Function Applies program voltage (12.5 V). Inputs address update clock. Selects operation mode. Inputs and outputs 8-bit data. Applies supply voltage (6 V).
2.1
OPERATION MODE FOR WRITING, READING, AND VERIFICATION OF PROGRAM MEMORY
If +6 V is applied to the VDD and +12.5 V to the VPP pin after PD17P207 has been placed in the reset status for a fixed time (VDD = 5V, RESET = Low level), PD17P207 enters program memory write, read, or verify mode. The MD0 to MD3 pins are used to set the operation modes listed in Table 2-2. Leave the pins not used for program memory writing, reading, or verification open or ground through pull-down resistors (470 ). (Refer to (2) PROM programming mode in PIN CONFIGURATION.)
Table 2-2. Operating Mode for Program Memory Writing, Reading or Verification
Operating Mode Specification Operating Mode VPP VDD MD0 H +12.5 V +6 V L L H Remark x: L or H MD1 L H L x MD2 H H H H MD3 L H H H Program memory address 0 clear mode Write mode Read/verify mode Program inhibit mode
13
PD17P207
2.2 PROGRAM MEMORY WRITE PROCEDURE
The program memory write procedure is as follows. High-speed program memory write is possible. (1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 s, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Write data in 1-millisecond write mode. (8) Set program inhibit mode. (9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9). (10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times 1 milliseconds. (11) Set program inhibit mode. (12) Supply a pulse to the CLK pin four times to update the program memory address by 1. (13) Repeat steps (7) to (12) to the last address. (14) Set program memory address 0 clear mode. (15) Change the voltages of VDD and VPP pins to 5 V. (16) Turn off the power supply. Steps (2) to (12) are illustrated below.
X-time repetition Reset Write Verify Additional data write Address increment
VPP VPP VDD GND
VDD
VDD+1 VDD GND CLK D0-D7 Hi-z Data input Hi-z
Data output
Hi-z
Data input
Hi-z
MD0
MD1
MD2
MD3
14
PD17P207
2.3 PROGRAM MEMORY READ PROCEDURE
(1) Ground the unused pins through pull-down resistors. The CLK pin must be low. (2) Supply 5 V to the VDD pin. The VPP pin must be low. (3) After waiting for 10 s, supply 5 V to the VPP pin. (4) Operate the MD0 to MD3 pins to set program memory address 0 clear mode. (5) Supply 6 V to the VDD pin and 12.5 V to the VPP pin. (6) Set program inhibit mode. (7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the CLK pin four times. (8) Set program inhibit mode. (9) Set program memory address 0 clear mode. (10) Change the voltages of VDD and VPP pins to 5 V. (11) Turn off the power supply. Steps (2) to (9) are illustrated below.
Reset
VPP VPP VDD GND
VDD
VDD+1 VDD GND 1 cycle
CLK
D0-D7
Hi-z
Data output
Data output
Hi-z
MD0
MD1
"L"
MD2
MD3
15
PD17P207
3. DIFFERENCES BETWEEN PD17P207 AND PD17201A/17207
The PD17P207 has a PROM to which the user can write a program in place of the internal mask ROM (program memory) of the PD17201A and 17207. Therefore, the PD17P207 is identical to PD17201A and 17207 except for the program memory and mask option. However, some of the electrical characteristics, such as supply current or VLCDC voltage of the
PD17P207, are different from that of the PD17201A and 17207.
The following table lists the differences between the PD17P207 and PD17201A/17207. For the details of the CPU and hardware of the PD17201A and 17207, refer to their Data Sheets.
Item Product Name Program Memory
PD17P207 -001
PD17P207 -002
One-Time PROM 0000H-0FFFH 4096 x 16 bits
PD17P207 -003
PD17201A
PD17207
Mask ROM 0000H-0BFFH 3072 x 16 bits 0000H-0FFFH 4096 x 16 bits
Pull-Up Resistor of RESET Pin
Not provided Provided Provided Not provided Any (mask option)
Main Clock Oscillator Circuit
Subclock Oscillator Circuit
Not provided Provided
Provided
VPP pin, PROM Programming Pin Supply Voltage (TA = -20 to +75C) Package
Not provided VDD = 2.2 to 5.5 V (at fX = 4 MHz)
VDD = 2.5 to 5.5 V (at fX = 4 MHz, TA = -20 to +75C) VDD = 2.4 to 5.5 V (at fX = 4 MHz, TA = -20 to +60C)
80-pin plastic QFP (14 x 20 mm)
16
PD17P207
4. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25C)
Parameter Supply Voltage Analog Supply Voltage Input Voltage Output Voltage Symbol VDD VADC VI VO Peak value REM pin rms value High-Level Output Current One pin (except REM) All pins (except REM) Peak value rms value Peak value rms value Peak value One pin Low-Level Output Current rms value IOL All pins (except REM) TA Tstg Peak value rms value 22.5 15 -20 to +75 -40 to +125 mA mA C C 5 mA -20 -7.5 -5 -22.5 -15 7.5 mA mA mA mA mA mA Conditions Rating -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -30 Unit V V V V mA
IOH
Operating Ambient Temperature Storage Temperature
Note
rms value = Peak value x Duty Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product.
Caution
CAPACITANCE (TA = 25C, VDD = 0 V)
Parameter Input Capacitance CIN2 Other than INT and RESET pins 10 pF Symbol CIN1 Conditions INT and RESET pins MIN. TYP. MAX. 10 Unit pF
RECOMMENDED OPERATING RANGES (TA = -20 to + 75C)
Parameter Symbol VDD1 Supply Voltage VDD2 VDD3 Main Clock Oscillation Frequency Subclock Oscillation Frequency fX fXT Conditions System clock fX = 4 MHz fX = 4 MHz, TA = -20 to + 60C System clock fX = 8 MHz System clock fXT = 32.768 kHz MIN. 2.5 2.4 4.5 2.0 1.0 TYP. 3.0 3.0 5.0 3.0 4.0 32.768 MAX. 5.5 5.5 5.5 5.5 8.0 Unit V V V V MHz kHz
17
PD17P207
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = -20 to +75C, VDD = 2.5 to 5.5 V)
Resonator Recommended Constants Item Oscillation Note 1 frequency (fX)
Note 2
Conditions
MIN. 1.0
TYP. 4
MAX. 8.0
Unit MHz
XIN
Note 3
XOUT
Ceramic Resonator
C1
C2
Oscillation stabilization time
From when VDD reaches the minimum oscillation voltage
4
ms
XIN
Note 3
XOUT
Oscillation frequency (fX) Note 1 C2
Note 2 Oscillation stabilization time
1.0
4
8.0
MHz
Crystal Resonator
C1
VDD = 4.5 to 5.5V
10 30
ms ms
Notes 1. The oscillation frequency is indicated only to express the oscillator characteristics. Refer to the AC characteristics for instruction execution time. 2. The oscillation stabilization time is the time required for stabilizing the oscillation after VDD is applied or the STOP mode is released. 3. The recommended resonators are shown in the table described later. SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS
Recommended Constants
Resonator
Item
Conditions
MIN.
TYP.
MAX.
Unit
XIN Crystal Resonator
XOUT
Oscillation frequency (fXT)
32.768
kHz
Oscillation stabilization time
5
10
s
Caution
When using the main system clock and the subsystem clock generators, in order to avoid wiring capacitance effects, the following notations must be read and observed for wiring the portion inside the dotted line in the table: * Wiring length must be minimized. * Do not cross with other signal lines. Do not wire close to a large current line. * Capacitors used in the oscillators must always be grounded to GND potential level. Never ground the grounding pattern having a large current flow. * Do not take the signal directly out of the oscillator. In order to reduce the power consumption, the subsystem clock oscillator employs a low amplification factor circuit. Because of this, the subsystem clock oscillator is more sensitive to noise than the main system clock oscillator. Therefore, when using the subsystem clock, wiring must be carefully planned.
18
PD17P207
RECOMMENDED RESONATORS Main System Clock : Ceramic Resonator
External Capacitance (pF) Manufacturer Part Name C1 CSA3.58MG CSA4.00MG CSA4.19MG MURATA Mfg. CST3.58MGW 30 30 30 Not required Not required Not required 33 33 33 18 39 C2 30 30 30 Not required Not required Not required 33 33 33 18 33 MIN. 2.0 2.0 2.0 2.0 MAX. 6.0 6.0 6.0 6.0 Oscillation Voltage Range (V) Remarks
CST4.00MGW
2.0
6.0
Built-in capacitor
CST4.19MGW
2.0
6.0
KBR3.58MS KYOCERA KBR4.0MS KBR4.19MS TOKO DAISHINKU CRHF4.00 PRS0400BCSAN
2.0 2.0 2.0 2.0 2.0
6.0 6.0 6.0 6.0 6.0
Main System Clock : Crystal Resonator
External Capacitance (pF) C1 KINSEKI 4.0 HC-49U-S 22 C2 22 Oscillation Voltage Range (V) MIN. 2.0 MAX. 6.0
Manufacturer
Frequency (MHz)
Holder
Remarks
19
PD17P207
DC CHARACTERISTICS (TA = -20 to +75C, VDD = VADC = 3 V)
Parameter Symbol VIH1 High-Level Input Voltage VIH2 VIL1 Low-Level Input Voltage VIL2 High-Level Input Leakage Current ILIH1 ILIH2 ILIL1 ILIL2 IOH1 High-Level Output Current IOH2 Low-Level Output Current IOL RP0A Built-In Pull-Up Resistor RRES A/D Absolute Precision A/D Resolution A/D Converter Current Consumption Comparator Error IDD1 IDD2 Supply Current IDD3 IDD4 IDD5
Note 3 Note 1 Note 2
Test Condition RESET and INT pins Other than RESET and INT pins RESET and INT pins Other than RESET and INT pins XTIN, XTOUT, XIN, and XOUT pins Other than XTIN, XTOUT, XIN, and XOUT pins XTIN, XTOUT, XIN, and XOUT pins Other than XTIN, XTOUT, XIN, and XOUT pins REM pin VOH = 1.8 V VOH = 2.7 V VOL = 0.3 V
MIN. 2.4 2.1 0 0
TYP.
MAX. 3 3 0.6 0.9 20 3 -20 -3
Unit V V V V
A A A A
mA mA mA
Low-Level Input Leakage Current
-7 -0.3 0.5 100 24
-15 -0.7 0.9 200 47 350 94 2 8
P0A0 to P0A3 pins RESET pins (PD17P207-001 only)
k k LSB Bits
IADC
60
120
A
In comparator mode X installed (fX = 4.19 MHz) XT not installed RUN mode HALT mode STOP mode X not installed or STOP mode XT installed (fXT = 32.768 kHz) RUN mode HALT mode
10 1.6
20 2.2 1.8
mV mA mA
3.0 400 20
10.0 600 40
A A A
Notes 1. P0A0 to P0A3, P0D0 to P0D3, and P1A0 to P1A2 pins 2. P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P0D0 to P0D3, P1A0 to P1A2, WDOUT, and REM pins 3. The specifications of the main STOP mode (sub-mounting) are the same as the sub-HALT mode (with the main clock oscillation stopped). LCD CHARACTERISTICS (TA = -20 to +75C, VDD = 3 V)
Parameter VLCDC Output Voltage LCD Reference Output Voltage Doubler Output Voltage Tripler Output Voltage LCD Common Output Current LCD Segment Output Current Symbol VLCDC VLCD0 VLCD1 VLCD2 ICOM ILCD Test Condition TA = 25C, R1 = R2 = 1 M External variable resistance (0 to 2.2 M) C1 to C4 = 0.47 F C1 to C4 = 0.47 F Output voltage deviation = 0.2 V Output voltage deviation = 0.2 V MIN. 0.5 0.8 1.9 2.85 30 5 2.0 3.0 TYP. 0.65 MAX. 0.8 1.8 Unit V V VLCD0 VLCD0
A A
20
PD17P207
AC CHARACTERISTICS (TA = -20 to +75C, VDD = 2.0 to 5.5 V)
Parameter Symbol Condition Data input VDD = 5 V10 % Data output SCK Input Cycle Time tKCY Data input Data output Data input VDD = 5 V10 % SCK Input High- and Low-Level Widths tKH, tKL Data output Data input Data output SI Setup Time (Vs. SCK) SI Hold Time (Vs. SCK) SCKto SO Output Delay Time INT High-and Low-Level Width RESET Low-Level Width P0A Low-Level Width tSIK tKSI tKSO CL = 100 pF 5.0 2.5 6.5 100 100 4.5 5 13 1.0 10 MIN. 2.0 TYP. MAX. Unit
s s s s s s s s
ns ns
s s s s
tIOH, tIOL tRSL tRLSL At standby release
50 50 10
SERIAL TRANSFER TIMING 3-line Serial I/O Mode:
t KCY t KL t KH
SCK
t SIK
t KSI
SI
Input data
t KSO
SO
Output data
21
PD17P207
DC PROGRAMMING CHARACTERISTICS (TA = 25C, VDD = 6.0 0.25V, VPP = 12.5 0.3V)
Parameter High-Level Input Voltage Symbol VIH1 VIH2 Low-Level Input Voltage Input Leakage Current High-Level Output Voltage Low-Level Output Voltage VDD Supply Current VPP Supply Current VIL1 VIL2 ILI VOH VOL IDD IPP MD0 = VIL, MD1 = VIH Conditions Other than CLK CLK Other than CLK CLK VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA VDD -1.0 0.4 30 30 MIN. 0.7 VDD VDD -0.5 0 0 TYP. MAX. VDD VDD 0.3 VDD 0.4 10 Unit V V V V
A
V V mA mA
Cautions 1. VPP must not exceed +13.5 V, including the overshoot. 2. Apply VDD before VPP and disconnect it after VPP.
22
PD17P207
AC PROGRAMMING CHARACTERISTICS (TA = 25C, VDD = 6.0 0.25V, VPP = 12.5 0.3V)
Parameter Address Setup Time
Note 2
Symbol Note 1 (vs.MD0) tAS tM1S tDS tAH tDH tDF tVPS tVDS tPW tOPW tMOS tDV tM1H tM1R tPCR tXH,tXL fX tI tM3S tM3H tM3SR tDAD tHAD tM3HR tDFR tRES tAS tOES tDS tAH tDH tDF tVPS tVCS tPW tOPW tCES tDV tOEH tOR - - - - - - - tACC tOH - - -
Conditions
MIN. 2 2 2 2 2 0 2 2 0.95 0.95 2
TYP.
MAX.
Unit
s s s s s
130
MD1 Setup Time (vs. MD0) Data Setup Time (vs. MD0) Address Hold Time Note 2 (vs.MD0) Data Hold Time (vs. MD0) MD0 Data Output Float Delay Time VPP Setup Time (vs. MD3) VDD Setup Time (vs. MD3) Initial Program Pulse Width Additional Program Pulse Width MD0 Setup Time (vs. MD1) MD0 Data Output Delay Time MD1 Hold Time (vs. MD0) MD1 Recovery Time (vs. MD0) Program Counter Reset Time CLK Input High-/Low- Level Width CLK Input Frequency Initial Mode Set Time MD3 Setup Time (vs. MD1) MD3 Hold Time (vs. MD1) MD3 Setup Time (vs. MD0) Address Address
Note 2 Data Output Delay Time Note 2
s s s
1.0
1.05 21.0
ms ms
s
1
MD0 = MD1 = VIL tM1H + tM1R 50 s 2 2 10 0.125
s s s s s
4 2 2 2 2 2 When data is read from program memory 0 2 2 10 130
MHz
s s s s s s s s s
Data Output Hold Time
MD3 Hold Time (vs. MD0) MD3 Data Output Float Delay Time Reset Setup Time
Notes 1. These symbols are the corresponding PD27C256A (maintenance product) symbols. 2. The internal address is incremented by 1 at the third falling edge of CLK (with four clocks constituting as one cycle). The internal address is not connected to any pin.
23
PD17P207
PROGRAM MEMORY WRITE TIMING
tRES VPP VDD GND VDD+1 VDD GND CLK D0 to D7 Hi-z tI MD0 tPW MD1 tPCR MD2 tM3S MD3 tM3H tM1S tM1H tM1R tMOS tOPW Data input tDS t OH Hi-z
Data output
tVPS
VPP
tVDS tXH
VDD
Hi-z tDF
Data input tDS tDH tAH
tXL
Hi-z tAS
Data input
Hi-z
tDV
PROGRAM MEMORY READ TIMING
tRES tVPS VPP VPP VDD GND VDD+1 VDD GND CLK tXL D0 to D7 tI MD0 Hi-z tDV tHAD Data output tDAD Data output tM3HR Hi-z tDFR
tVDS
VDD
tXH
MD1
"L" tPCR
MD2 tM3SR MD3
24
PD17P207
5. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14 20)
A B
64 65
41 40
detail of lead end
CD
S Q R
80 1
25 24
F G H P I
M
J
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.20.2 20.00.2 14.00.2 17.20.2 1.0 1.8 0.350.10 0.15 0.8 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 2.7 0.1250.075 55 3.0 MAX. INCHES 0.913 +0.009 -0.008 0.787 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.0050.003 55 0.119 MAX. S80GF-80-3B9-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
25
PD17P207
6. RECOMMENDED SOLDERING CONDITIONS
When mounting the PD17P207 by soldering, soldering should be performed under the following recommended contitions. For details on recommended soldering conditions, refer to the information document "Semconductor Device Mounting Technology Manual" (C10535E). For other soldering methods, please cousult with NEC sales personnel.
Table 6-1. Conditions for Surface Mounting
PD17P207GF-001-3B9 : 80-pin plastic QFP ( 14 x 20 mm) PD17P207GF-002-3B9 : 80-pin plastic QFP ( 14 x 20 mm) PD17P207GF-003-3B9 : 80-pin plastic QFP ( 14 x 20 mm)
Recommended Conditions Reference Code
Soldering Method
Soldering Conditions
Infrared Reflow
Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of times: 2 max., Number of days: 7Note (after that, prebaking is necessary at 125 C for 20 hours) Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. Package peak temperature: 215C Time: 40 seconds max. (200C min.), Number of times: 2 max., Number of days: 7Note (after that, prebaking is necessary at 125 C for 20 hours) Products other than those supplied in thermal-resistant tray (magazine, taping, and non-thermal-resistant tray) cannot be baked in their packs. Soldering bath temperature: 260 C max., Time: 10 seconds max., Number of times: 1 Preheating temperature: 120 C max. (package surface temperature) Number of days: 7Note (after that, prebaking is necessary at 125 C for 20 hours) Pin temperature: 300C max., Time: 3 seconds max. (per device)
IR35-207-2
VPS
VP15-207-2
Wave Soldering
WS 60-207-1
Partial Heating
Note
Number of days after unpacking the dry pack. Storage conditions are 25C and 65 %RH max. Do not use different soldering methods together (however, pin partial heating can be performed with other soldering methods).
Caution
26
PD17P207
APPENDIX A. MICROCONTROLLER FAMILY FOR HIGH-FUNCTION REMOTE CONTROLLER WITH LCD
Item
Product Name ROM Capacity
PD17201A
3072 x 16 bits (Mask ROM)
PD17207
4096 x 16 bits (Mask ROM) 336 x 4 bits 136 segments max. LED output is high-active.
PD17P207
4096 x 16 bits (One-Time PROM)
RAM Capacity LCD Controller/Driver Infrared Remote Controller Carrier Generator Number of I/O Ports External Interrupt (INT) Timer 2 channels
19 1 8-bit timer : 1 Watch timer : 1
Watchdog Timer Serial Interface Stack Main System Clock Subsystem Clock Main System Clock Subsystem Clock
Internal (WDOUT output) 1 channel 5 levels (3 levels for multiplexed interrupt) 4 s (4 MHz: with ceramic or crystal oscillator) 488 s (32.768 kHz: with crystal osciallator) 2.5 to 5.5 V 2.2 to 5.5 V 2.0 to 5.5 V 2.4 to 5.5 V Note
Instruction Execution Time
Supply Voltage (TA = -20 to +75C)
Standby Function Pakcage
STOP, HALT 80-pin plastic QFP
Note
TA = -20 to + 60C
27
PD17P207
APPENDIX B. DEVELOPMENT TOOLS
To develop the programs for the PD17P207, the following development tools are available: Hardware
Name In-Circuit Emulator Remarks IE-17K, IE-17K-ET, and EMU-17K are the in-circuit emulators used in common with the 17K series microcomputer. IE-17K and IE-17K-ET are connected to a PC-9800 series or IBM PC/ATTM as the host machine with RS-232C. EMU-17K is inserted into the expansion slot of a PC-9800 series. By using these in-circuit emulators with a system evaluation board corresponding to the microcomputer, the emulators can emulate the microcomputer. A higher level debugging environment can be provided by using man-machine interface SIMPLEHOSTTM. EMU-17K also has a function by which you can check the contents of data memory realtime. This is an SE board for PD17201A, 17207, and 17P207. It can be used alone to evaluate a system or in combination with an in-circuit emulator for debugging. EP-17201GF is an emulation probe for PD17201A, 17207, and 17P207. When used with EV-9200G-80, it connects an SE board to the target system. EV-9200G-80 is a conversion socket for 80-pin QFP (14 x 20 mm) and is used to connect EP-17201GF to the target system. AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers corresponding to PD17P207. By connecting program adapter AF-9808A to this PROM programmer, PD17P207 can be programmed.
IE-17K IE-17K-ET EMU-17K
Note 1 Note 2
SE Board (SE-17207) Emulation Probe (EP-17201GF) Conversion Socket (EV-9200G-80 Note 3) PROM Programmer (AF-9703 Note 4, AF-9704 Note 4, AF-9705 Note 4, AF-9706 Note 4) Program Adapter (AF-9808 Note 4)
AF-9808A is an adapter that is used to program PD17P207, and is used in combination with AF-9703, AF-9704, AF-9705, or AF-9706.
Notes 1. Low-cost model: External power supply type 2. This is a product from IC Corp. For details, consult IC Corp. 3. Two EV-9200G-80s are supplied with the EP-17201GF. Five EV-9200G-80s are optionally available as a set. 4. These are products from Ando Electric. For details, consult Ando Electric.
28
PD17P207
Software
Name Outline Host Machine OS Media Supply Order Code
5" 2HD AS17K is an assembler that can be used in common with the 17K series products. When developing the program of the PD17P207, AS17K is used in combination with a device file (AS17201 or AS17207). PC-9800 series MS-DOSTM 3.5" 2HD
S5A10AS17K S5A13AS17K S7B10AS17K S7B13AS17K S5A10AS17201 S5A10AS17207 S5A13AS17201 S5A13AS17207 S7B10AS17201 S7B10AS17207 S7B13AS17201 S7B13AS17207 S5A10IE17K S5A13IE17K S7B10IE17K S7B13IE17K
17K Series Assembler (AS17K)
5" 2HC IBM PC/AT PC DOSTM 3.5" 2HC
Device File AS17201 AS17207
AS17201 is a device file for PD17201A. AS17207 is a device file for PD17207. These are used in combination with an assembler for the 17K series (AS17K).
5" 2HD PC-9800 series MS-DOS 3.5" 2HD
5" 2HC IBM PC/AT PC DOS 3.5" 2HC
Support Software (SIMPLEHOST)
SIMPLEHOST is a software package that enables manmachine interface on the TM Windows when a program is developed by using an in-circuit emulator and a personal computer.
5" 2HD PC-9800 series MS-DOS 3.5" 2HD Windows 5" 2HC IBM PC/AT PC DOS 3.5" 2HC
Remark
The corresponding OS versions are as follows:
OS MS-DOS PC DOS Windows Version Ver. 3.30 to Ver. 5.00A Note Ver. 3.1 to Ver. 5.0 Ver. 3.0 to Ver. 3.1
Note
Note
Ver. 5.00/5.00A of MS-DOS and Ver. 5.0 of PC DOS have a task swap function, but this function cannot be used with this software.
29
PD17P207
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
30
PD17P207
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
31
PD17P207
[MEMO]
SIMPLEHOST is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
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